Preface. Section I: Design & Test of Memories. 1. Opening Pandora's Box. 2. Static Random Access Memories. 3. Multi-Port Memories. 4. Silicon On Insulator Memories. 5. Content Addressable Memories. 6. Dynamic Random Access Memories. 7. Non-Volatile Memories. Testing II: Memory Testing. 8. Memory Faults. 9. Memory Patterns. Section III: Memory Self Test. 10. BIST Concepts. 11. State Machine BIST. 12. Micro-Code BIST. 13. BIST and Redundancy. 14. Design For Test and BIST. 15. Conclusions. Appendices. Appendix A. Further Memory Fault Modeling. Appendix B. Further Memory Test Patterns. Appendix C. State Machine HDL. References. Glossary/Acronyms. Index. About the Author.

Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully.
High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test.

High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.