Bültmann & Gerriets
System-On-Chip: Next Generation Electronics
von Bashir M. Al-Hashimi
Verlag: Institution of Engineering & Technology
Reihe: Materials, Circuits and Device
Gebundene Ausgabe
ISBN: 978-0-86341-552-4
Erschienen am 15.01.2006
Sprache: Englisch
Format: 236 mm [H] x 160 mm [B] x 56 mm [T]
Gewicht: 1451 Gramm
Umfang: 944 Seiten

Preis: 192,50 €
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Klappentext
Inhaltsverzeichnis

This book highlights both the key achievements of electronic systems design targeting SoC implementation style, and the future challenges presented by the continuing scaling of CMOS technology.




  • Part 1: System-level design

  • Chapter 1: Multi-criteria decision making in embedded system design

  • Chapter 2: System-level performance analysis - the SymTA/S approach

  • Chapter 3: Analysis and optimisation of heterogeneous real-time embedded systems

  • Chapter 4: Hardware/software partitioning of operating systems: focus on deadlock avoidance

  • Chapter 5: Models of computation in the design process

  • Chapter 6: Architecture description languages for programmable embedded systems

  • Part 2: Embedded software

  • Chapter 7: Concurrent models of computation for embedded software

  • Chapter 8: Retargetable compilers and architecture exploration for embedded processors

  • Chapter 9: Software power optimisation

  • Part 3: Power reduction and management

  • Chapter 10: Power-efficient data management for dynamic applications

  • Chapter 11: Low power system scheduling, synthesis and displays

  • Chapter 12: Power minimisation techniques at the RT-level and below

  • Chapter 13: Leakage power analysis and reduction for nano-scale circuits

  • Part 4: Reconfigurable computing

  • Chapter 14: Reconfigurable computing: architectures and design methods

  • Part 5: Architectural synthesis

  • Chapter 15: CAD tools for embedded analogue circuits in mixed-signal integrated Systems-on-Chip

  • Chapter 16: Clock-less circuits and system synthesis

  • Part 6: Network-on-chip

  • Chapter 17: Network-on-chip architectures and design methods

  • Chapter 18: Asynchronous on-chip networks

  • Part 7: Simulation and verification

  • Chapter 19: Covalidation of complex hardware/software systems

  • Chapter 20: Hardware/software cosimulation from interface perspective

  • Chapter 21: System-level validation using formal techniques

  • Part 8: Manufacturing test

  • Chapter 22: Efficient modular testing and test resource partitioning for core-based SoCs

  • Chapter 23: On-chip test infrastructure design for optimal multi-site testing

  • Chapter 24: High-resolution flash time-to-digital conversion and calibration for system-on-chip testing

  • Chapter 25: Yield and reliability prediction for DSM circuits


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