This book explores classical field programmable gate array (FPGA) architectures and their supporting tools; evaluates recent proposals related to FPGA architectures, including the use of network-on-chips (NoCs); examines reconfigurable processors that merge concepts borrowed from the reconfigurable domain into processor design; and exploits FPGAs for high-performance systems, efficient error correction codes, and high-bandwidth network routers with built-in security. The book also expounds on emerging technologies to improve FPGA routing structures and create non-volatile configuration flip-flops, providing valuable insight into the future potential of reconfigurable systems.

Pierre-Emmanuel Gaillardon is a research associate at the Laboratory of Integrated Systems, École Polytechnique Fédérale de Lausanne, Switzerland. He holds an undergraduate degree from École Supérieure de Chimie Physique Électronique de Lyon, France; an M.Sc from Institut National des Sciences Appliquées de Lyon, France; and a Ph.D from Laboratoire d'Électronique des Technologies de l'Information (CEA-LETI), Grenoble, France and the University of Lyon, France. Starting January 2016, he will assume an assistant professorship with the Electrical and Computer Engineering Department, University of Utah, Salt Lake City, USA. Previously, he was a research assistant at CEA-LETI, and a visiting research associate at Stanford University, Palo Alto, California, USA. Dr. Gaillardon is an associate editor of the IEEE Transactions on Nanotechnology, a reviewer for several journals and funding agencies, a technical program committee member for many conferences, and the recipient of the C-Innov 2011 Best Thesis and Nanoarch 2012 Best Paper awards.

Adaptive Packing for Design Space Exploration of FPGA Logic Block Architectures. Improving Fault Tolerance of SRAM-Based FPGAs in Harsh Radiation Environments. Zero-Overhead FPGA Debugging. Tree-Based FPGA Routing Architectures. And-Inverter Cones. Embedded Networks-on-Chip for FPGAs. Design Methodologies for Reconfigurable NoC-Based Embedded Systems. Circuits and Architectures for Low-Power FPGAs. Reconfigurable Processors and Multicore Architectures. Partially Reconfigurable Processor for Wireless Receiver Applications. A Heterogeneous Architecture for Biomolecular Simulation. Design of High-Performance Error-Correcting Codes Using FPGA. Reconfigurable Network Router Security. Low-Power FPGAs Based on Resistive Memories. Spintronic-Memory-Based Reconfigurable Computing. Architectures and CAD Tools for 3D FPGAs.