This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

• Most up-to-date coverage of design for testability.
• Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
• Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.

Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).

Chapter 1 - IntroductionChapter 2 - Design for TestabilityChapter 3 - Logic and Fault Simulation Chapter 4 - Test Generation Chapter 5 - Logic Built-In Self-TestChapter 6 - Test CompressionChapter 7 - Logic DiagnosisChapter 8 - Memory Testing and Built-In Self-TestChapter 9 - Memory Diagnosis and Built-In Self-RepairChapter 10 - Boundary Scan and Core-Based TestingChapter 11 - Analog and Mixed-Signal TestingChapter 12 - Test Technology Trends in the Nanometer Age