Asynchronous System-on-Chip Interconnect describes the use of an entirely asynchronous system-bus for the modular construction of integrated circuits. Industry is just awakening to the benefits of asynchronous design in avoiding the problems of clock-skew and multiple clock-domains, an din parallel with this is coming to grips with Intellectual Property (IP) based design flows which emphasise the need for a flexible interconnect strategy. In this book, John Bainbridge investigates the design of an asynchronous on-chip interconnect, looking at all the stages of the design from the choice of wiring layout, through asynchronous signalling protocols to the higher level problems involved in supporting split transactions. The MARBLE bus (the first asynchronous SoC bus) used in a commercial demonstrator chip containing a mixture of asynchronous and synchronous macrocells is used as a concrete example throughout the book.

1. Introduction.- 2. Asynchronous Design.- 3. System Level Interconnect Principles.- 4. The Physical (Wire) Layer.- 5. The Link Layer.- 6. Protocol Layer.- 7. Transaction Layer.- 8. MARBLE: A Dual-Channel Split Transfer Bus.- 9. Evaluation.- 10. Conclusion.- Appendix A: MARBLE Schematics.- A1 Bus interface top level schematics.- A2 Initiator interface controllers.- A3 Target interface controllers.- A4 Bus drivers and buffers.- A5 Latch controllers.- A6 Centralised bus control units.- References.